An arithmetic unit that executes a numerical arithmetic process is expected to process more complicated arithmetic operations at a higher speed than ever. In some cases, the arithmetic unit may include a plurality of arithmetic sections such as, for example, CPUs (Central Processing Units) in order to meet the requirements for higher speed processing of arithmetic operations. The arithmetic unit is allowed to process a plurality of arithmetic operations in parallel using the plurality of CPUs.
A program that the arithmetic unit executes is stored in a storage such as a memory or the like. In some case, a plurality of arithmetic sections may share one storage. When the plurality of arithmetic sections intend to simultaneously read out the program stored in the same address space in the storage that the plurality of arithmetic sections share, an access competition may occur. A circuit that arbitrates access order in accordance with a rule which has been defined in advance when the access competition has occurred is called an arbitrator circuit. The plurality of arithmetic sections is allowed to continuously execute the program with no error even when the competition has occurred by accessing to the storage via the arbitrator circuit.
As a device for testing whether the arbitrator circuit arbitrates the access order in accordance with the rule which has been defined in advance, a competition testing apparatus is proposed. The competition testing apparatus falsely makes a competition occur using the arbitrator circuit and evaluates the operation of the arbitrator circuit upon occurrence of the access competition.
In some cases, the length of wiring between one arithmetic section and the storage may be different from the length of wiring between another arithmetic section and the storage. A lag in dummy timing which is caused by the difference in wiring length increases with reducing a cycle of a signal in which it propagates from each arithmetic section to the storage. In the case that the lag in timing is large, it may become difficult to control the access from each arithmetic section to the storage so as to make the access competition occur using the arbitrator circuit.
A technique relating to installing false access signal generating means for falsely making an access competition occur is disclosed in Japanese Laid-open Patent Publication No. 2008-134807. It may become possible to favorably make the access competition occur owing to installation of the false access signal generating means.